One of the Optical Proximity Correction (OPC) process is a model-based optical proximity correction method, which adjusts photomask data so that the pattern resulting on the wafer is a close replica of a target pattern. An essential element of model-based OPC is a computational model of the patterning process. The computational model describes all or some aspects of: optical projection, reactions and diffusion of chemicals in the photoresist, and etching of the wafer. The computational model usually has parameters that need to be determined empirically. These parameters are determined by printing test patterns on wafers using the lithography equipment and processes (such as lithography and etch) that need to be modeled. Critical dimensions of the patterns (such as photoresist and etched wafer) resulting on the test wafer are measured. Some parameters of the model are adjusted until the difference between the predictions of the model and the patterns printed on the wafer are minimized. This process is called “calibration” of the model. Next critical step for obtaining computational models is the verification and the monitoring of these models in production. Without the model verification and monitoring, OPC may not be accurate.
The prior art described in the following U.S. Patents describe several devices and patterns placed in cut-lines (or equivalently scribe lines) to monitor and measure device characteristics and performance in production. However, the prior art does not include placing optical proximity corrected (OPC-ed) test and verification structures. Typical structures and devices mentioned in the prior art are functional small circuits to test and monitor electrical performance and programmed defects to test defect printability.    1. Stine, et al., “System and method for product yield prediction using a logic characterization vehicle,” U.S. Pat. No. 6,834,375, Dec. 21, 2004.    2. Stine, et al., “System and method for product yield prediction using device and process neighborhood characterization vehicle,” U.S. Pat. No. 6,795,952, Sep. 21, 2004.    3. Iwasa, et al., “Semiconductor integrated circuit,” U.S. Pat. No. 5,703,381, Dec. 30, 1997.    4. Sugasawara, “Process monitor circuitry for integrated circuits,” U.S. Pat. No. 6,124,143, Sep. 26, 2000.    5. Kim, et al., “Method for manufacturing a semiconductor device and semiconductor device with overlay mark,” U.S. Pat. No. 6,803,292, Oct. 12, 2004.    6. Cai, et al., “System and method of providing mask defect printability analysis,” U.S. Pat. No. 6,873,720, Mar. 29, 2005.
The prior art described in the following U.S. Patents do not take model verification and monitoring into account. The model describing lithography process and exposure tool in the prior art is based on SEM measurements and images of photoresist patterns, and usually for one dose and defocus condition.    1. Ivanovic, et al., “Automatic calibration of a masking process simulator,” U.S. Pat. No. 6,768,958, Jul. 27, 2004.    2. Ivanovic, et al., “Automatic calibration of a masking process simulator,” U.S. patent application Ser. No. 10/829,408, Apr. 20, 2004.    3. Garza, et al., “Comparing aerial image to SEM of photoresist or substrate pattern for masking process characterization,” U.S. Pat. No. 6,078,738, Jun. 20, 2000.    4. Laidig, et al., “Method of two dimensional feature model calibration and optimization,” U.S. patent application Ser. No. 10/266,922, filed Oct. 9, 2002.    5. Garza, et al., “Comparing aerial image to actual photoresist pattern for masking process characterization,” U.S. Pat. No. 6,081,659, Jun. 27, 2000.
As indicated above, computational models utilized in optical proximity correction processes must be accurate and precise. However, there exists no process which provides an accurate computational method which is also verified. Accordingly, there is a need for a new and improved computational model verification process that improves the accuracy and precision of such computational models.